1. Field of the Invention
The present invention relates to a current control circuit used in a dynamic random access memory (referred to hereinafter as DRAM) device to control current which is supplied from a data bit clamping circuit to a bit line sense amplifier.
2. Description of the Prior Art
Generally, a DRAM device comprises a plurality of memory blocks, each of which includes a plurality of DRAM cells. In order to make it more convenient for the user to operate, the DRAM device has been designed in such a manner that all the memory blocks, a part of the memory blocks or only one of the memory blocks can be refreshed.
The DRAM device includes a bit line sense amplifier for sensing and amplifying bit data on a bit line, a data bit clamping circuit for supplying current to the bit line sense amplifier, and a current control circuit for switching the current which is supplied from the data bit clamping circuit to the bit line sense amplifier. When the DRAM device is conducting a refresh operation, however, the current control circuit allows the current to be supplied to the bit line sense amplifier regardless of the refresh mode by memory blocks, resulting in unnecessary power consumption of the DRAM device. The problem with such a conventional current control circuit for a sense amplifier will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, the construction of a conventional current control circuit is schematically shown. As shown in this drawing, the conventional current control circuit comprises a pair of NMOS transistors Q1 and Q2 connected to first and second current paths between a data bit clamping circuit 10 and a bit line sense amplifier 12, respectively. The NMOS transistors Q1 and Q2 are adapted to open/close the first and second current paths according to a logic state of a current control signal from an input line 11, respectively. The current control signal from the input line 11 is generated from a global decoder (not shown) and becomes high in logic when at least one of the memory blocks is refreshed. In response to the current control signal from the input line 11, the NMOS transistors Q1 and Q2 are operated when the corresponding memory block is conducting the refresh operation, to allow the current to be supplied to the bit line sense amplifier 12 regardless of the refresh mode of a different memory block. For this reason, the unnecessary power consumption occurs in the DRAM device.